The present disclosure relates to methods for manufacturing a semiconductor device; and, more particularly, to a method for forming contact electrodes in a semiconductor device.
Generally, in designing and/or manufacturing semiconductor devices, employing a single layer for locating wiring on a semiconductor substrate provides little freedom in designing a desired wiring pattern. For example, in this single layer context, if a designer expands an actual length of wiring, the designer may severely restrict the layout of the semiconductor device.
In contrast, employing multiple layers for wiring enables a highly efficient layout design for a semiconductor device. That is, since each semiconductor layout can be determined without having to consider spots where wiring passes over the semiconductor substrate, the integration of the semiconductor device is enhanced. As a result, the size of the semiconductor device can be reduced or minimized. Further, since employing multiple layers makes it possible to design the wiring more freely and easily, the wiring resistance and the current capacity can be configured with more freedom.
Micromachining techniques have been developed recently. These developments have occurred along with increased integration and increased capability of integrated semiconductors. A chemical mechanical polishing (CMP) technique is one of the newly developed techniques. The CMP technique is used for LSI manufacturing processes; particularly in such functions as: (a) the planarization of an insulating layer, (b) forming a metal plug, and/or (c) forming a buried wiring for a multiple layer wiring process. This CMP technique is described in U.S. Pat. No. 4,944,836.
However, as the integration of semiconductor devices increases, limitations and drawbacks in forming a gate electrode having a small critical dimension are encountered. For example, as the critical dimension of the gate electrode decreases, a short channel effect occurs in which a threshold voltage becomes small due to a shorter length between a source channel and a drain channel.
Further, as the gate electrode becomes smaller, the insulating layer for the gate electrode becomes thin. As a result, the threshold voltage of the gate electrode also becomes small by a reverse narrow width effect.
It is known to use a conventional lithography process to manufacture a gate electrode having a narrow line width by using a notch profile with the use of a photolithographic pattern. However, this known process entails preparing a mask having a minimized device pattern for patterning the corresponding gate electrode. It is, therefore, indispensable to develop a light source for exposing, or an exposing device for minimizing, the mask and for exposing the photoresist pattern.